Nano-Friendly Computing Engines for Cognitive Tasks

NA FCOG 2012–2017
Academy of Finland
Budget DFT: 407 272 €

NA FCOST 2012–2015
Academy of Finland
Budget DFT: 300 000 €

Two-terminal memristive memory is a nanoelectronic component that is lithography-friendly: devices are self-aligned as they are formed to wire crossings of perpendicular wires, and can be fabricated on top of CMOS integrated circuits. The project aims at performing effective computing using nanoscale memristor arrays. A leading idea is to perform computing with memristors so as to maximally utilize the intrinsic physical characteristics of the devices. The research targets on-chip cognitive processing with emphasis on overcoming the power-efficiency wall exhibited with conventional digital computing. The project is ongoing, below we list selected activities carried out within the project so far.

Together with collaborators, means of computing with a memristor/CMOS hybrid circuit were developed, and the fabricated analog memristor/field-programmable analog array (FPAA/memristor) hybrid circuit was experimented with [1]. The FPAA/analog memristor hybrid circuit is first of a kind in the world. Content-associative memory (CAM) provides a means to locate data of interest within a memory array, and is important in the context of the research. The CAM concept can be broadened to cover also partial hits (Associative CAM, ACAM), so that the strength of the hit is proportional to the number of matching bits in the input vector. An associative search operation enables the retrieval of input vectors among noisy data, because a partial hit is sufficient to be interpreted as a match.

The amount of tolerated mismatch in the data vectors can be controlled through a programmable threshold. Associative memory architectures and their memristive implementation were studied in [2]. CMOS/memristor hybrid circuits were identified as a promising candidate for realization of large-scale associative memories. In [3], an integrated circuit implementation of a content addressable memory architecture that realizes both ACAM and Willshaw operation modes was reported. The chip was implemented in 180 nm CMOS and has a die area of 5×5 mm2. The size of the memory array is 512×512 cells and the chip has a 64-bit hit memory for each array row, and 8 bits of input memory per array column. The built-in row and column circuitry can perform logic operations on the contents of the row and column memories. Hit vectors are extracted either with a tunable threshold circuit, or with a row-parallel WTA. The paper demonstrated how the ACAM chip can be used to carry out semantic processing on random vectors, using binding (XOR) and sumset (a concatenation of selected bits from both vectors) operations. In [4] we showed how nondeterministic finite automata can be computed in the autoassociative CAM circuit reported in [3].

  1. M. Laiho, J. O. Hasler, J. Zhou, C. Du, W. Lu, E. Lehtonen, J. H. Poikonen, ”FPAA/Memristor Hybrid Computing Infrastructure”, IEEE Transactions Circuits and Systems I, in press.
  2. E. Lehtonen, J. H. Poikonen, M. Laiho, P. Kanerva, “Large-Scale Memristive Associative Memories”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 2014.
  3. M. Laiho, J. K. Poikonen, E. Lehtonen, M. Pänkäälä, J. H. Poikonen, P. Kanerva, “A 512×512-Cell Associative CAM/Willshaw Memory with Vector Arithmetic”, accepted to International Symposium on Circuits and Systems, 2015.
  4. J. H. Poikonen, E. Lehtonen, M. Laiho, T. Knuutila, “Implementation of nondeterministic finite automata in an autoassociative CAM”, accepted to International Symposium on Circuits and Systems, 2015.

Research Partners

Ask more

Mika Laiho

Academy Research Fellow, Adjunct prof. of Parallel Computing & Systems
+358 (0)50 436 7577